The harsh operating environments in automotive, military, and avionics applications place extreme technical demands on integrated circuits, which must withstand high voltages and currents, extreme temperatures and humidity, vibration, radiation, and a variety of other stresses. To provide the features and functions required in applications such as security, entertainment, telematics, control, and human-machine interfaces, system engineers are rapidly adopting high-performance electronics. With the increasing use of precision electronics, systems have become more complex and more susceptible to electrical disturbances, including overvoltage, latch-up conditions, and electrostatic discharge (ESD) events. The Electronic circuits used in these applications require high reliability and high tolerance to system failures, so designers must consider environmental factors and the limitations of the device itself when selecting a device.
In addition, every integrated circuit has some absolute maximum ratings specified by the manufacturer; these ratings must be designed with care to ensure reliable performance and published specifications. Beyond these absolute maximum ratings, operating parameters are not guaranteed; built-in ESD, overvoltage, or latch-up protections may even fail, resulting in device (and possibly further) damage or failure.
This article describes the challenges engineers face when designing analog switches and multiplexers into modules used in harsh environments, and provides some general solution recommendations that circuit designers can use to protect vulnerable devices. In addition, some new integrated switches and multiplexers are introduced with improved overvoltage protection, latch-up immunity and fault protection to handle common stress conditions.
Standard Analog Switch Architecture
To fully understand the effects of a fault condition on an analog switch, one must first look at its internal structure and operating limits.
Standard CMOS switches (Figure 1) use N- and P-channel MOSFETs as switching elements, digital control logic, and driver circuitry. N and P-channel MOSFETs are connected in parallel, allowing bidirectional operation and extending the analog input voltage range to the supply rails while keeping the on-resistance fairly constant over the entire signal range.
Figure 1. Standard Analog Switch Circuit
The signal source, drain, and logic control terminals are designed with clamping diodes for positive and negative source voltages to provide ESD protection, as shown in Figure 1. In normal operating mode, these diodes are reverse biased so no current will flow unless the signal exceeds the supply voltage. The dimensions of these diodes vary by process, but are generally small in design to minimize leakage current during normal operation.
Analog switches are controlled as follows: N-channel devices turn on when the gate-source voltage is positive and turn off when this voltage is negative; P-channel devices are switched by complementary The N-channel devices are turned on at the same time. The switch is turned on and off by applying positive and negative source voltages to the two gates, respectively.
When the voltage on the gate is fixed, the effective drive voltage of the two transistors varies proportionally with the polarity and amplitude of the analog signal passing through the switch. The dotted line in Figure 2 shows that as the input signal approaches the supply voltage, there is always a device whose channel begins to saturate, causing the device’s on-resistance to increase dramatically. However, the paralleled devices compensate each other around the supply rail voltage, so the end result is full rail-to-rail switching with on-resistance that remains relatively constant over the signal range.
Figure 2. Standard Analog Switch RON Diagram
Absolute Maximum Ratings
Design attention should be paid to the switching power requirements specified in the device data sheet to ensure optimum performance, operation, and lifetime. Unfortunately, actual operation involves power failures, voltage transients in harsh environments, and system or user failures, making it impossible to always meet data sheet requirements.
As long as the input voltage to the analog switch exceeds the supply voltage, even if the power supply is turned off, the built-in ESD protection diodes become forward biased, allowing large currents to flow, which would exceed those ratings. When forward biased, the conduction current of these diodes is not limited to a few tens of milliamps, and if this forward current is not limited, it may cause device damage. More seriously, the damage caused by the fault is not limited to the switch, but can also affect downstream circuits.
The “Absolute Maximum Ratings” section of the data sheet (Figure 3) describes the maximum stress conditions that the device can withstand; it is important to note that these are only maximum ratings. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Designers should always follow good engineering practice and allow for margins in the design. The example here is taken from the standard switch/multiplexer data sheet.
Figure 3. “Absolute Maximum Ratings” Section of the Data Sheet
In this example, the VDD to VSS parameter is rated at 18 V. This rating depends on the switch manufacturing process and design architecture. All voltages above 18V must be completely isolated from the switch, otherwise the intrinsic breakdown voltage of the components associated with the process will be exceeded, which may damage the device and cause unreliable operation.
Whether or not power is applied, the upper voltage limit at the input of an analog switch is usually determined by an ESD protection circuit that can fail due to a fault condition.
Figure 4. Analog Switch—ESD Protection Diode
Analog input voltage limits are limited to 0.3 V beyond VDD and VSS, while digital input voltage limits are limited to 0.3 V beyond VDD and GND. When the analog input exceeds the supply voltage, the built-in ESD protection diode becomes forward biased and begins to conduct. As described in the Absolute Maximum Ratings section, overvoltages on IN, S, or D are clamped by internal diodes. While currents above 30 mA can pass through the internal diodes without noticeable effect, device reliability and lifetime may be reduced, and electromigration effects (ie, gradual movement of metal atoms on the wire) may occur over time. . When a strong current flows through the metal path, there is an interaction between the moving electrons and the metal atoms on the wire, forcing the metal atoms to move along with the electrons. Over time, this can lead to an open or short circuit.
When designing a switch into a system, it is important to consider the various potential failures that can occur in the system due to device failure, user error, or environmental influences. The next section will discuss how fault conditions exceeding the absolute maximum ratings of a standard analog switch can damage the switch or cause it to malfunction.
Common Fault Conditions, System Stresses, and Protection Methods
Failure conditions occur for different reasons; some of the most common system stresses and their actual sources are listed in Table 1:
Some stresses may not be avoided. Whatever the source of stress is, what is more important is how to deal with its effects. The following Q&A session covers the three fault conditions of overvoltage, latch-up and ESD events and provides some common protection methods.
What is an overvoltage condition?
An overvoltage condition occurs when an analog or digital input exceeds the Absolute Maximum Ratings. The following three examples highlight some common issues that designers should consider when using analog switches.
1. Power is missing and there is a signal on the analog input (Figure 5)
In some applications, the input signal from a remote location may still be present when power to the module is lost. When power is lost, the supply rails may go to ground, or one or more of the supply rails may be left floating. If the power supply goes to ground, the input signal can forward bias the internal diode, so the current at the input of the switch will flow to ground, which can damage the diode if the current is not limited.
Figure 5. Failure path
If a power loss leaves the power supply floating, the input signal can power the device through an internal diode. Therefore, the switch (and possibly any other device powered from its VDD supply) may power up.
2. An overvoltage condition on the analog input.
When the analog signal exceeds the supply voltages (VDD and VSS), the supply is pulled within the diode drop of the fault signal. The internal diode is forward biased and current flows from the input signal to the power supply. Overvoltage signals can also flow through the switch and damage downstream devices. This can be seen by considering the case of a P-channel FET (Figure 6).
Figure 6. FET switch
The P-channel FET can only be turned on when the gate-source voltage is negative. When the switch gate is equal to VDD, the gate-source voltage is positive, so the switch is turned off. In an unpowered circuit, when the switch gate is equal to 0V or the input signal exceeds VDD, the gate-source voltage is now negative, so the signal will flow through the switch.
3. Apply a bipolar signal to a switch powered by a single supply
This condition is similar to the overvoltage condition described earlier. This fault occurs when the input signal drops below ground, causing the diode between the signal input and ground to forward bias and begin to conduct current. When an AC signal biased at 0 V DC is applied to the switch input, the parasitic diode may be forward biased for a portion of the negative half cycle of the input waveform. This happens if the input sine wave falls below about –0.6 V, at which point the diode will conduct and clip the input signal, as shown in Figure 7.
Figure 7. Clipping
What is the best way to handle an overvoltage condition?
All three examples above are the result of the analog input exceeding the power supply (VDD, VSS, or GND). Simple protection against these conditions includes adding external resistors, adding Schottky diodes to the power supply, and adding blocking diodes on the power supply.
A current-limiting resistor can be placed in series between the switch path and the external circuit (Figure 8). The resistor must be large enough to limit the current to about 30 mA (or as specified by the absolute maximum ratings). The obvious disadvantage is that the RON per channel increases (∆RON), which ultimately increases the overall system error. Also, for applications using multiplexers, faults on the circuitry external to the shutdown channel can appear at the drain, causing errors in the other channels.
Figure 8. Resistor Diode Protection Network
A Schottky diode connected between the analog input and the power supply provides protection, but increases leakage current and capacitance. These diodes prevent the input signal from exceeding the supply voltage by more than 0.3V to 0.4V, ensuring that the internal diodes do not become forward biased and therefore do not generate on-current. Diverting current through the Schottky diode can protect the device, but care must be taken not to overstress the external device.
A third method of protection requires a blocking diode in series with the power supply (Figure 9), thereby blocking current flow through the internal diode. A fault on the input causes the power supply to float, and the maximum positive and negative input signals become the power supply. The device should be fault tolerant as long as the power supply does not exceed the absolute maximum ratings of the process. The disadvantage of this method is that the analog signal range is reduced due to the diode on the power supply. Additionally, signals applied to the input may pass through the device and affect downstream circuits.
Figure 9. Blocking Diode in Series with Power Supply
While each of these protection methods has advantages and disadvantages, they all require external components, take up additional board space, and incur additional costs. In high channel count applications, this may be especially pronounced. To eliminate external protection circuits, designers should seek integrated protection solutions that can withstand these faults. Analog Devices offers a wide variety of switch/multiplexer families with integrated power-off, overvoltage, and negative signal protection.
What are the preventive measures?
The ADG4612 and ADG4613 from Analog Devices feature low on-resistance and low distortion, making them ideal for data acquisition systems that require high precision. The on-resistance curve is very flat over the entire analog input range, ensuring excellent linearity and low distortion performance.
The ADG4612 family of devices provides power-down protection, over-voltage protection, and negative signal processing functions that standard CMOS switches cannot handle.
The switch remains open when there is no power. The switch input presents a high impedance, limited current flow, which can cause damage to the switch or downstream circuitry. The ADG4612 is useful for applications where an analog signal may be present at the switch input before power is applied, or where the user has no control over the power-up sequence of the power supply. In the disconnected condition, signal levels up to 16 V are shielded. Also, if the analog input signal level is higher than VDD by VT, the switch will open.
Figure 10. ADG4612/ADG4613 Switch Architecture
Figure 10 shows a block diagram of the power-off protection architecture for this family of devices. The architecture continuously monitors the source and drain inputs of the switch and compares them with the power supplies VDD and VSS. In normal operation, the switch behaves the same as a standard CMOS switch supporting full rail-to-rail operation. However, when a fault condition occurs at the source or sink input by a threshold voltage above the supply, an internal fault circuit detects the overvoltage condition and places the switch in isolation mode.
Analog Devices also offers multiplexers and channel protectors that are tolerant to +40 V/–25 V overvoltage conditions with (±15 V) power applied to the device and without power Overvoltage conditions exceeding +55V/–40V. These devices are specifically designed to handle failures caused by power outage conditions.
Figure 11. High Voltage Fault Protected Switch Architecture
These devices consist of N-channel, P-channel, and N-channel MOSFETs connected in series, as shown in Figure 11. When one of the analog inputs or outputs exceeds the supply voltage, one of these MOSFETs is turned off and the multiplexer input (or output) appears open circuit, while the output is clamped to within the supply rails, preventing overvoltage Damage any circuits after the multiplexer. This protects the multiplexer, the circuitry it drives, and the sensor or signal source driving the multiplexer. When power is missing (such as a disconnected battery or power failure) or temporarily disconnected (such as a rack system), all transistors are turned off and current is limited to below nanoamp levels. 8:1 and differential 4:1 multiplexers such as the ADG508F, ADG509F, and ADG528F have this capability.
The ADG465 single-channel protector and the ADG467 octal-channel protector have the same protection architecture as these fault-protected multiplexers, but without the switching functionality. When powered, the channel is always on, but in the event of a fault, the output is clamped to within the power supply voltage.
What is a latched condition?
Latch-up can be defined as a low-impedance path between supply rails caused by triggering parasitic devices. Latch-up occurs in CMOS devices: Intrinsic parasitic devices form the PNPN SCR structure, and latch-up occurs when one of the two parasitic base-emitters is transiently forward biased (Figure 12). The conduction of the SCR results in a continuous short circuit between the power supplies. The consequences of triggering a latch-up condition are severe: in the “best” case, it causes the device to fail, requiring a power cycle to restore the device to normal operation; in the worst case, if the current is not limited, the device (and the power supply) will be destroyed.
Figure 12. Parasitic SCR results: a) Device b) Equivalent circuit
The fault and overvoltage conditions described earlier are common causes of latch-up conditions. If the signal at the analog or digital input exceeds the supply voltage, the parasitic transistor turns on. The collector current of this transistor causes a voltage drop across the base-emitter of the second parasitic transistor, which turns the second transistor on, resulting in a self-sustaining path between the power supplies. Figure 12(b) clearly shows the SCR circuit structure formed between Q1 and Q2.
Such events can trigger a latch for a period of time. A brief transient, spike, or ESD event may be enough to cause the device to latch up.
Additionally, if the supply voltage exceeds the absolute maximum ratings of the device, it can cause the internal PN junction to break down and trigger the SCR.
The second trigger mechanism is when the supply voltage rises enough to break down an internal PN junction and inject current into the SCR.
What’s the best way to handle a latched condition?
The protection methods against latch-up include the same protection methods recommended for overvoltage conditions. By adding current-limiting resistors in the signal path, adding Schottky diodes to the power supplies, and placing diodes in series with the power supplies (as shown in Figures 8 and 9), these can help prevent current from flowing through the parasitic transistors, thereby preventing the SCR trigger.
With multiple power supplies, the switches may also have power-up sequencing issues that can exceed their absolute maximum ratings if not handled properly. Improper power-up sequencing can cause internal diodes to conduct and trigger latch-up. By connecting external Schottky diodes between the supplies, it ensures that when multiple supplies are applied to the switch, VDD is always within the diode drop (0.3 V for Schottky diodes) of these supplies, preventing violations maximum rating, thus effectively preventing SCR conduction.
What are the preventive measures?
As an alternative to external protection circuits, some ICs are fabricated using an epitaxial layer process that increases the resistance between the substrate and the N-well in the SCR structure. The increased resistance means that the SCRs are triggered under harsher stress, making the device less susceptible to latch-up. One example is Analog Devices’ iCMOS® process, which has spawned the ADG121x, ADG141x, and ADG161x switch/multiplexer families.
For applications that require a latch-up-proof solution, new switches and multiplexers with trench isolation technology guarantee latch-up-free high-voltage industrial applications operating up to ±20 V. The ADG541x and ADG521x family of devices are designed for instrumentation, automotive applications, avionics and other harsh environments prone to latch-up. The process places an insulating oxide layer (trentch) between the N-channel and P-channel transistors of each CMOS switch. The oxide layer provides complete vertical and horizontal isolation between the devices. Therefore, parasitic PN junctions between transistors are eliminated, resulting in a switching circuit that is completely free of latch-up.
Figure 13. Trench isolation in latch-up protection
It is industry practice to divide the input and output susceptibility to latch-up according to the amount of overcurrent that fans in and fan-out of the I/O pins under that overvoltage condition before the internal parasitic resistance develops a voltage drop sufficient to maintain the latch-up condition.
100 mA is generally considered sufficient. Devices in the ADG5412 latch-up proof family can tolerate ±500 mA on 1-ms pulses without failure. Analog Devices’ latch-up test is performed in accordance with EIA/JEDEC-78 (IC Latch-Up Test).
What is an ESD event?
Generally speaking, ESD is one of the most common voltage transients on devices, and is defined as “a single, fast, high-current electrostatic charge transfer between two objects with different potential differences.” This phenomenon is very common: when we walk over an insulating surface such as a carpet, the charge builds up, and then if we touch the grounded part of the device, a momentary high-current discharge occurs through the device.
The high voltages and peak currents generated by ESD events can damage ICs. Its effects on analog switches include reduced reliability over time, reduced switching performance, increased channel leakage current, or complete device failure.
ESD events can occur at any stage of an IC’s life cycle, from manufacturing to testing, handling, OEM users, and end-user operations. To evaluate the IC’s robustness to various ESD events, electronic pulse circuits were identified that model the following simulated stress environments: Human Body Model (HBM), Induced Discharge Model (FICDM), and Machine Discharge Model (MM).
What’s the best way to handle an ESD event?
During production, assembly, and storage, ESD protection methods such as maintaining an electrostatically safe work area can be used to avoid any accumulation of electrical charges. Such an environment and the personnel in it can often be carefully controlled, but the environment in which the device is then used may be beyond control.
Analog switch ESD protection circuits usually take the form of placing diodes between the analog and digital inputs and the source, while power protection circuits also take the form of placing diodes between the sources, as shown in Figure 14.
Figure 14. Analog Switch ESD Protection Circuit
Protection diodes clamp voltage transients and direct current to the source. The disadvantage of these types of protection devices is that they add capacitance and leakage current to the signal path during normal operation, which may be undesirable in some applications.
For applications that require greater protection from ESD events, discrete devices such as Zener diodes, metal oxide varistors (MOVs), transient voltage suppressors (TVS), and diodes are often available. However, these devices create increased capacitance and leakage currents on the signal lines, which can lead to signal integrity issues; this means that designers need to carefully consider and trade off performance and reliability.
What are the preventive measures?
Most of ADI’s switch/multiplexer products meet HBM levels of at least ±2 kV, and some devices go further in performance with HBM ratings up to ±8kV. The HBM specification of ADG541x series devices is ±8-kV, the FICDM specification is ±1.5-kV and the MM specification is ±400-V, which realizes the perfect combination of high voltage performance and high ESD protection performance, and is a well-deserved leader in the industry.
Failure is more likely when the switch or multiplexer input comes from a remote source. Improper system power-up sequence design or system hot-plugging may cause overvoltage. In harsh electrical operating environments, transient voltages caused by poor connections or inductive coupling can damage components if unprotected. In addition, failures can also occur in the event of a power failure such that the power connection is lost while the switch input is still connected to the analog signal. These fault conditions can cause significant damage and result in high repair costs. While a variety of protection design techniques can be employed to address these failures, cost and board space increase, and there are often trade-offs in switching performance; and even implementing external protection circuits does not always protect downstream circuits . While analog switches and multiplexers are often the electronic components most exposed to various fault conditions, it is important to understand how these devices behave when exposed to conditions that exceed their absolute maximum ratings.
Some switch/multiplexer products, such as the devices mentioned here, have integrated protection circuits that eliminate the need for external protection circuits, reducing component count and cost in board designs. In high channel count applications, the savings will be more significant.
Ultimately, by using switches with fault protection, overvoltage protection, latch-up resistance, and high ESD ratings, high reliability products that meet industrial requirements will be available to the satisfaction of customers and end users.
About the Author
Michael Manning[firstname.lastname@example.org]graduated from the National University of Galway, Ireland, with a master’s degree in applied physics and electrical engineering. He joined Analog Devices in 2006 in the Switch/Multiplexer division in Limerick, Ireland. Before that, Michael worked for five years as a design and applications engineer in the automotive applications division of ALPS Electric in Japan and Sweden.